Current radio frequency (RF) receiver integrate circuits (ICs) often convert analog signals associated with RF input signals to digital samples and then perform digital processing on these digital samples. In addition, some digital processors operate on data frames that are generated by aggregating a number of digital samples together into a data frame. As such, digital samples are generated from the RF input signals, combined into data frames, and then processed by one or more digital processors to generate digital output data representing the information contained within the RF transmissions. As part of this digital frame processing, digital clocks are utilized to operate digital circuitry within the digital processors. Periodic current pulses associated with this digital circuitry and the digital frame processing can generate frequency domain interference that interferes with the RF signals being received and processed by the RF receiver ICs.
FIG. 1 (Prior Art) is a block diagram of an embodiment 100 for an RF receiver IC that performs digital frame processing. Looking first to the analog portion of embodiment 100, the RF front-end 104 is configured to receive RF input signals 102, for example, an RF signal spectrum received from an antenna. The RF front-end 104 processes these RF input signals 102 and outputs analog signals associated with the RF input signals 102 to the analog-to-digital converter (ADC) 106. It is noted that the RF front-end 104 can provide filtering, gain adjustment, and/or other desired analog processing to the RF input signals 102. The RF front-end 104 can also be configured to receive a channel select signal 105 that determines a channel within the RF signal spectrum that will be tuned by the RF receiver IC 100. For example, the channel can be one of a number of different channels broadcast within a frequency band (e.g., AM radio, FM radio, television broadcasts, etc.). Further, in some embodiments, the RF front-end 104 can include a mixer and a local oscillator that are used to down-convert the RF signal spectrum to a lower frequency, such as a zero or non-zero intermediate frequency (IF), prior to the analog signals being converted to digital samples by the ADC 106. For other embodiments, no mixers are used, and the RF signal spectrum is directly digitized by the ADC 106.
Looking now to the digital portion of embodiment 100, the ADC 106 receives the analog signals from the RF front-end 104 and converts them into digital data samples. The digital data samples are then received and digitally processed by digital signal processor (DSP) 118 to generate digital output data 120 that can be output to additional circuitry and/or processing blocks. The digital signal processor 118 in part includes a frame buffer 110, a digital frame processor 112, a frame rate controller 114, and a digital clock 116. The digital signal processor 118 can also include digital channel filters, digital decimation, and/or other digital processing blocks.
In operation, the digital data samples from the ADC 106 are stored in the frame buffer 110, which can be a memory circuitry such as dynamic random access memory (DRAM) circuitry or other desired data storage medium. The digital frame processor 112 receives digital data frames that each include a block of digital samples from the frame buffer 110 and processes these digital data frames to generate the digital output data 120. The frame rate controller 114 provides frame control signal 115 to the digital frame processor 112 to indicate when to start the processing of each data frame and thereby control the frame processing rate (FFRATE). The digital clock 116 provides digital clock signals 117 at a digital clock frequency (FDSP) to the frame rate controller 114 and to the digital frame processor 112. The frame rate controller 114 toggles the logic levels of the frame control signal 115 at periodic intervals associated with cycles of the digital clock 116, and the digital frame processor uses the frame control signal 115 to start its processing of each digital data frame. The digital frame processor 112 uses the cycles of the digital clock 116 to perform its digital processing operations. Periodic current pulses due to the digital switching within the digital frame processor 112 as it operates to process the data frames causes frequency domain interference 130 that can interfere with the RF input signals 102 being received by the RF front-end 104 and thereby degrade the performance of the RF receiver IC 100.
FIG. 2A (Prior Art) is a signal diagram of an embodiment 200 for the frame control signal 115 and digital switching currents 204 associated with the digital frame processor 112 in FIG. 1 (Prior Art). The frame control signal 115 toggles logic levels at periodic intervals having a frame rate (FFRATE) such that the period (T) of each cycle is T=1/FFRATE. In one embodiment, the rising edges of the frame control signal 115 are used as frame processing start indicators as represented by arrows 202, although both edge transitions could also be used if desired. At each of these rising edge transitions, the digital frame processor 112 begins processing of a new frame of data samples. As shown with respect to the digital switching currents 204, each of these frame processing cycles causes digital switching currents that will follow a similar pattern for each frame processing cycle. Initially, for each processed frame, these currents 204 will rise in portions 206 as the data frame is processed. These currents 204 then drop to low levels in portions 208 as the digital frame processor 112 enters an idle mode after it completes frame processing within each frame processing cycle. The repeating current pulses in portions 208 caused by the digital frame processing leads to frequency domain interference 130 that can degrade performance.
FIG. 2B (Prior Art) is a frequency signal diagram of an embodiment 250 for frequency domain interference 130 from the periodic current pulses depicted in FIG. 2A (Prior Art) that are generated from the digital switching operations during digital frame processing. Frequency domain interference 252 is associated with the base frame rate (FFRATE) due to the digital switching within the digital frame processor 112 and the resulting current pulses shown in FIG. 2A (Prior Art) for the digital switching currents 204. Further, frequency domain interference is also associated with harmonics of the base frame rate frequency (FFRATE), such as interferences with respect to the second harmonic (2FFRATE) 254, the third harmonic (3FFRATE) 256, the fourth harmonic (4FFRATE) 258, and the fifth harmonic (5FFRATE) 260. This frequency domain interference 103 can potentially overlap and interfere with frequencies of interest within the RF input signals 102 and thereby degrade performance of the RF receiver IC 100.